The traditional method for interfacing between various boards in a multiboard system is by using a standard system bus. A good bus standard provides the guidelines necessary for an independent designer to design various boards or option cards that will work together. System buses generally utilize address bits, data bits and control logic, plus additional logic for bus arbitration, system control and power. Important criteria in choosing a microprocessor bus is the number of bits on the data bus, the width of the address bus, the types of interrupts and the types of data transfer control, i.e., synchronous or asynchronous. System buses may be multiplexed or nonmultiplexed and many follow standard Motorola architecture. Motorola style buses typically have a read-write line and a data strobe and use memory-mapped input/output.
Many system buses are able to handle multiple masters. A multimaster bus allows several coprocessors to share the system bus and requires additional arbitration logic. In addition, buses with data paths larger than 8 bits, generally allow data transfers that use part of the data path. A bus with a 32 bit data path, for example, may allow transfers of single bytes or 16-bit words in addition to full 32 bit transfers.
System buses are either synchronous or asynchronous. A synchronous bus operates in synchronization with a system bus clock. An asynchronous bus allows signals to be asynchronous to the system clock and operates by using various strobes to initiate signals. For example, a Motorola system microprocessor provides a data transfer acknowledgment signal which indicates that the memory is ready to perform a read or write operation after it has been requested by the processor of a direct memory accessing peripheral. Once the data has been transferred to a dynamic random access memory (DRAM), the data may be printed onto a page. In many cases, a full page of DRAM is unavailable for printing due to the high cost of the DRAM so smaller DRAM pages had to be designed. One method of providing a smaller amount of DRAM onto a page is by using band buffers.
Among the problems associated with interface systems in a multiboard system are that the hardware on the various boards is not always compatible. The interface must then be designed in order to specifically provide for the problems created by the hardware inconsistencies.
The present invention provides an interface system between an incompatible print font coprocessor and controller board. In the described embodiment, the font coprocessor comprises a Blue Point 100 font scaling chip which supports all the features needed to render scalable characters including functions specific to character rendering. The Blue Point 100 (BP100) follows standard Motorola architecture for bus arbitration. The controller board comprises the controller of an existing Okidata (Oki) printer known as the OL800. The OL800 is an eight page per minute printer which uses a proprietary LED array to write images on a photosensitive drum which in turn, transforms the image to a single sheet of paper stock. Unlike the BP100 chip, the Oki OL800 controller follows its own arbitration scheme which is not the same as standard Motorola architecture. It is therefore necessary, to design a tailored interface to allow direct memory access between the Blue Point 100 and the OL800 controller without violating either system's architecture scheme.